1. Field of the Invention
The present invention relates to an input circuit and a semiconductor integrated circuit having the input circuit, and more particularly to an input circuit applicable to a semiconductor integrated circuit having a delay locked loop (DLL) circuit that needs a long lock-on time.
2. Description of the Related Art
Recent high-speed, highly-integrated semiconductor circuits require a phase-locked clock signal for controlling objective circuits. For example, a synchronous dynamic random access memory (SDRAM), which operates at a high speed of 100 MHz or over, employs a DLL circuit to supply a signal whose phase is synchronized with an external clock signal, to output circuits or output buffers.
By the way, it is strongly required to reduce the power consumption of semiconductor integrated circuits such as SDRAMs. One technique of reducing the power consumption of an SDRAM is to deactivate an input circuit of the SDRAM while the SDRAM is in a self-refresh mode.
Namely, the input circuit of the SDRAM is stopped in response to a self-refresh mode signal to reduce power consumption during a self-refresh mode. Note that circumferential conditions may change before and after the self-refresh mode. For example, a power source voltage and ambient temperature may greatly change before and after the self-refresh mode. In this case, the DLL circuit that receives an output of the input circuit spends (needs) many dummy cycles to restore a lock-on (steady) state. Such dummy cycles waste time.
Prior and related arts and the problems thereof will be explained later with reference to accompanying drawings.
An object of the present invention is to shorten the lock-on time of an internal circuit or a synchronous circuit. Another object of the present invention is to speedily establish a steady state of a DLL circuit without dummy cycles after the completion of a self-refresh operation.
According to the present invention, there is provided an input circuit comprising an input buffer for receiving an external signal (external control signal) and outputting an internal signal (internal control signal); and a detection circuit for detecting whether or not the external signal is provided, wherein the input buffer outputs the internal signal when an output of the detection circuit indicates that the external signal is provided.
The internal signal may be supplied to an internal circuit that spends (requires) a predetermined time to establish a steady state. The internal circuit may be a delay locked loop circuit.
Further, according to the present invention, there is also provided a semiconductor integrated circuit having an input circuit for receiving an external clock signal and outputting an internal clock signal, and an internal circuit that receives the internal clock signal and spends a predetermined time to establish a steady state, wherein the input circuit comprises an input buffer for generating the internal clock signal from the external clock signal; and a detection circuit for detecting whether or not the external clock signal is provided, wherein the input buffer outputs the internal clock signal when an output of the detection circuit indicates that the external clock signal is provided.
The semiconductor integrated circuit may be a synchronous dynamic random access memory, and the internal circuit may be a delay locked loop circuit for controlling an output timing of an output circuit that outputs data in synchronization with the external clock signal. The input circuit may further comprise an internal oscillator for generating pulses at predetermined intervals during a self-refresh mode, to carry out a self-refresh operation, the input buffer may output the internal clock signal during the self-refresh mode when the external clock signal is provided, and the input buffer may be deactivated when the external clock signal is stopped.
The delay locked loop circuit may comprise a delay circuit for receiving the internal clock signal, delaying the internal clock signal by a predetermined amount, and outputting the delayed signal; a dummy delay circuit for receiving the internal clock signal, delaying the internal clock signal by the same amount as that of the delay circuit, and outputting the delayed signal; a delay control circuit for providing the delay circuit and dummy delay circuit with the same delay amount; and a phase comparison circuit for receiving a reference signal corresponding to the internal clock signal and an objective signal made by passing the output of the dummy delay circuit through predetermined circuits, and supplying pulses whose number corresponds to a phase difference between the reference signal and the objective signal, to the delay control circuit to control the delay amount of the delay circuit and the dummy delay circuit.
The delay locked loop circuit may further comprise a frequency divider that receives the internal clock signal and outputs an output signal to the dummy delay circuit and the reference signal to the phase comparison circuit.
According to the present invention, there is provided an input circuit comprising an input buffer for receiving an external control signal and providing an internal control signal; and a timing signal generator for generating a timing signal, wherein the input buffer provides the internal control signal for a predetermined period in response to the timing signal.
According to the present invention, there is also provided a semiconductor integrated circuit comprising an input circuit for receiving an external clock signal and providing an internal clock signal; and an internal circuit that receives the internal clock signal and takes a predetermined time to establish a steady state, wherein the input circuit includes an input buffer for generating the internal clock signal from the external control signal and a timing signal generator for generating a timing signal; and the input buffer provides the internal clock signal for a predetermined period in response to the timing signal.
The timing signal generator may include an oscillator. The timing signal generator may further include a frequency divider. The frequency divider may change a frequency dividing ratio after a predetermined period. The frequency divider may lower a frequency of the timing signal as time passes. The timing signal generator may further include a pulse width adjuster for adjusting a pulse width of the timing signal.
The input circuit may further comprise an internal control signal output unit for receiving the internal control signal from the input buffer and providing the internal control signal for internal circuits; and a synchronous circuit for receiving the internal control signal from the input buffer and providing the internal control signal output unit with a timing signal synchronized with the internal control signal.
The semiconductor integrated circuit may be a synchronous DRAM and the oscillator may serve as a self-refresh oscillator. The timing signal generator may not generate a timing signal during a self-refresh operation.
Further, according to the present invention, there is provided an input circuit comprising an input buffer for receiving an external control signal and providing an internal control signal; a timing signal generator for generating a timing signal; and a control signal detection circuit for providing a detection signal indicating whether or not the external control signal is activated, wherein the input buffer provides the internal control signal according to the timing signal and the detection signal.
Further, according to the present invention, there is also provided a semiconductor integrated circuit comprising an input circuit for receiving an external clock signal and providing an internal clock signal; and an internal circuit that receives the internal clock signal and takes a predetermined time to establish a steady state, wherein the input circuit includes an input buffer for providing the internal clock signal according to the external clock signal, a timing signal generator for generating a timing signal, and a clock signal detection circuit for providing a detection signal indicating whether or not the external clock signal is activated; and the input buffer provides the internal clock signal according to the timing signal and the detection signal.
The input buffer may provide the internal clock signal for a predetermined period and then may stop the internal clock signal in response to the timing signal. The input circuit may include a synchronous circuit for synchronizing the timing signal with the detection signal. The clock signal detection circuit may be stopped in response to the timing signal.
The timing signal generator may include an oscillator. The timing signal generator may further include a frequency divider. The frequency divider may change a frequency dividing ratio after a predetermined period. The frequency divider may lower a frequency of the timing signal as time passes. The timing signal generator may further include a pulse width adjuster for adjusting a pulse width of the timing signal. The timing signal generator may generate the timing signal by lowering a frequency of the external clock signal.
In addition, according to the present invention, there is provided an input circuit comprising an input buffer for receiving an external control signal and providing an internal control signal; a timing signal generator for generating a timing signal; and a control signal detection circuit for providing a detection signal indicating whether or not the external control signal is activated, wherein the input buffer provides the internal control signal according to the timing signal and the detection signal; and the internal control signal is started and stopped in response to the timing signal.
Further, according to the present invention, there is also provided a semiconductor integrated circuit comprising an input circuit for receiving an external clock signal and providing an internal clock signal; and an internal circuit that receives the internal clock signal and takes a predetermined time to establish a steady state, wherein the input circuit includes an input buffer for providing the internal clock signal according to the external clock signal, a timing signal generator for generating a timing signal, and a clock signal detection circuit for providing a detection signal indicating whether or not the external clock signal is activated; the input buffer provides the internal clock signal according to the detection signal; and the internal clock signal is started and stopped in response to the timing signal.
The input circuit may further include an input buffer controller for generating an input buffer control signal according to the detection signal; the input buffer may provide the internal clock signal according to the input buffer control signal; and the input buffer controller may include a latch, generate the input buffer control signal according to the detection signal, latch the same, and release the latched state according to the timing signal. The timing signal generator may start to operate in response to the detection signal and stop to operate after providing the timing signal. The timing signal generator may include an oscillator. The timing signal generator may generate the timing signal by lowering a frequency of the external clock signal.